Fabrication of low leakage-current backside illuminated photodiodes

ABSTRACT

Ultra-low leakage current backside-illuminated semiconductor photodiode arrays are fabricated using a method of formation of a transparent, conducting bias electrode layer that avoids high-temperature processing of the substrate after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and an ohmic backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer and a portion of the thickness of heavily-doped crystalline silicon layer formed within, and near the back of, the substrate during the gettering process.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of U.S. application Ser. No. 10/842,938, filed May 10, 2004, which is a continuation of U.S. application Ser. No. 10/295,285, filed Nov. 15, 2002, now U.S. Pat. No. 6,734,416, which is a divisional of U.S. application Ser. No. 09/839,641, filed Apr. 20, 2001, now U.S. Pat. No. 6,670,258, which claims benefit of U.S. provisional application Ser. No. 60/198,912, filed Apr. 20, 2000.

TECHNICAL FIELD

The present invention relates to electromagnetic radiation detectors, and more specifically to backside-illuminated semiconductor photodiode arrays.

BACKGROUND

A typical photodiode array includes a semiconductor substrate of a first conductivity type, having a front side formed with an array of doped regions of a second, opposite conductivity type, and an opposing back side that includes a heavily-doped bias electrode layer of the first conductivity type. For simplicity, the frontside doped regions are referred to below as gates, independent of their function as anodes or cathodes. Similarly, the abbreviation BEL is used to denote the backside bias electrode layer.

To provide a framework for the discussion below, an example of a photodiode array is used below in which the frontside doped gate regions have p-type conductivity, the substrate is n-type, and the backside bias electrode layer is, accordingly, a heavily-doped n-type layer. All statements and claims herein are equally true if the conductivity types of all the layers are reversed and the corresponding changes are made to the polarities of the charge carriers, applied voltages and electric fields.

Typically, the gate and bias electrode layers are formed internally to the crystalline semiconductor substrate. They are therefore native to and homostructural with the substrate. In most implementations, an external gate contact, formed from one or more non-native, heterostructural, conducting layers external to the substrate, is formed over a portion of each of the frontside gates. Similarly, one or more non-native, heterostructural, external back contacts may be formed over all, or a portion of, the backside bias electrode layer. In the case of silicon substrates, the gate contacts are usually formed from one or more metals, metal-silicon intermetallic compounds, or deposited, heavily-doped polysilicon, or a combination of a plurality of these materials. In the present context, polysilicon is considered to be both non-native and heterostructural to the crystalline silicon substrate. Similarly, silicon dioxide (SiO₂), the amorphous “native oxide” of silicon, is both non-native and heterostructural to the substrate in this context. Back contacts to silicon photodiode arrays may use the same materials or one or more transparent conducting materials such as indium-tin oxide, which is an amorphous typically non-stoichiometric mixture of indium oxide and tin oxide. In many applications, an array of readout circuits is also formed on the front surface of the substrate.

A potential difference, referred to as a reverse bias, can be applied between the gate and the bias electrode layer to produce a depletion region within the substrate extending into the substrate from the p-n junction between the gate on the front side and the substrate. Hence, a photodiode is effected by the gate, the substrate and the BEL. External gate contacts or back contacts are ancillary elements provided to facilitate electrical connections to the photodiode array, not essential components thereof.

Such a photodiode array may be configured either in a frontside-illuminated mode to receive photons from the front side or in a backside-illuminated mode to receive photons from the backside. The frontside-illuminated mode, however, usually results in a lower external quantum efficiency (ratio of photocarriers collected to incident photons) than the backside-illuminated mode, because the conducting elements of the gate contacts and the readout circuits (if provided) reduce the active photosensitive area of the array on the front side. In comparison, the entire back side can be used to collect incoming radiation when properly configured. All other factors being equal, enhanced photosensitivity results in increased signal-to-noise ratio. In single-particle radiation detection applications using either direct (intrinsic) detection in the substrate or indirect detection (e.g., using scintillators as discussed below), enhanced photosensitivity results in improved particle energy resolution. In addition, conducting lines and other physical features such as steps in dielectric thickness on the front side can scatter light into the photosensitive areas of adjacent photodiodes, thereby reducing image contrast. Contrast degradation modifies the modulation transfer function of the array and can reduce the useful spatial resolution of the array. Therefore, backside illuminated photodiode arrays are frequently used in imaging applications to improve photosensitivity, signal-to-noise ratio, particle energy resolution and spatial resolution.

In a backside-illuminated photodiode, photocurrent is typically generated by band-to-band absorption. Photons with energy greater than the bandgap of the semiconductor substrate enter the back of the substrate and are absorbed, producing electron-hole pairs. If an electron-hole pair is generated outside the depletion region of a gate, the minority carrier (a hole in the example above) may diffuse to the edge of the depletion region beneath one of the gates. The electric field within the depletion region “collects” the hole by accelerating it towards the gate. If, however, a photon is absorbed within the depletion region of a gate, the electric field “collects” the hole as above, but accelerates the electron towards the undepleted substrate, or, if the substrate is fully depleted below a gate, towards the backside bias electrode layer. In either case, the photocurrent will flow through the photodiode and the external circuitry that maintains the bias between the gate and the bias electrode layer. If readout circuitry is provided on same semiconductor substrate, the circuit elements associated with each gate will produce a signal that represents a mathematical function of the photocurrent, the quantity of charge caused by the photon absorption, or a combination of both.

In low light-level imaging applications such as night photography, nuclear medical imaging, photon medical imaging, x-ray computed tomography and ballistic photon detection, it is critical for photodiode arrays simultaneously to exhibit high external photon conversion efficiency (defined as the ratio of photocarriers collected to photons incident on the back surface of the substrate) and extremely low reverse-bias leakage currents. For brevity, “quantum efficiency” is used below to denote external photon conversion efficiency, and “leakage current” is used to denote reverse-bias leakage current.

In low light-level imaging systems, the input optical signal often is in the form of short pulses, a few nanoseconds to a few microseconds in duration. For these applications, it is highly beneficial for the photodiodes to have short pulse response times, often referred to collectively as transition times or, singly, as rise and fall times, in the rough order of magnitude range of 10 to 100 ns or less. The signal processing system associated with the photodiode arrays typically “shapes” the output pulse by integrating the photocurrent generated within a time window of fixed duration in the same order of magnitude as the length of the photopulse.

Photodiode arrays with one or more long transition times produce output photocurrent pulses significantly longer than the input photopulse. These long photocurrent pulses produce smaller output pulses from the signal processing electronics than do those from faster photodiode arrays. Therefore, slow photodiode arrays may may result in low output signals from the signal processing electronics and therefore degrade the signal-to-noise ratio of the image. In applications with higher photon flux rates, e.g., x-ray computed tomography, the signal processing electronics may respond to the average photocurrent collected by a pixel over a time interval of fixed duration, longer than the duration of a single optical pulse. For these applications, longer transition times than those required for efficient single pulse detection may be acceptable.

To achieve high quantum efficiency, the bias electrode layer should be thin enough to be transparent to the incident radiation, yet sufficiently conductive to provide an equipotential surface on the back surface of the substrate adequate to maintain uniform depletion over the entire area beneath each gate.

The bias electrode layer should also have a low density of crystallographic defects and be free from deep-level impurities. If these criteria are met, the BEL will exhibit long enough minority-carrier lifetimes to minimize recombination of photocarriers generated within the BEL, thereby maximizing the efficiency of collection of photocarriers generated therein The BEL will therefore not be an optical “dead layer.”

The pulse response times of the photodiodes can be minimized by using semiconductor substrates of high resistivity in the approximate range of 5 to 25 kΩ-cm, operated under reverse bias conditions sufficient to fully deplete the substrate under the gates. Under such full-depletion conditions, the electric field of the depletion region extends to the bias electrode layer on the back side.

Achieving ultra-low leakage current densities, e.g., below about 1 nA/cm² at room temperature, of the individual photodiodes requires reduction of the contributions to the total leakage current by (1) the substrate; (2) the back contact structure (including the bias electrode layer and any additional layers formed thereon); (3) the front surface regions between the gate regions and between the outer gates and the surrounding regions; and (4) the edges of the substrate, formed when the substrate is “diced” to form individual photodiode array chips.

The bulk generation current of the substrate may be reduced by “gettering,” an elevated-temperature process, typically performed at 1000° C. or higher for silicon substrates, in which strained, damaged or heavily-doped layers, singly or in combination, on the back surface of the substrate attract and capture impurities or crystallographic defects. Crystallographic defects may also be annihilated by recombination during the gettering process. The strained, damaged or heavily-doped “gettering layer” or layers is subsequently removed, thereby removing the absorbed impurities and defects. Once the substrate has been gettered, further high-temperature processes should be avoided, to prevent introduction of new impurities or generation of additional defects. All subsequent chemical processing and handling of the substrate should be scrupulously clean to avoid re-contamination.

Front surface generation currents in silicon photodiode arrays are usually minimized by using silicon dioxide (SiO₂) layers thermally grown under conditions known to produce low-leakage surfaces. These oxides are typically grown prior to, or concurrently with, the gettering process. Low-temperature (below 400° C.) treatments may be performed after gettering to optimize surface leakage.

Minimizing leakage currents associated with the back contact structure requires dealing with a number of contradictory requirements. As discussed above, the bias electrode layer must be thin enough to be transparent. Such thin layers, however, are easily damaged, and damaged regions may generate leakage current very efficiently. Under fully depleted conditions, the bias electrode layer must be contain enough electrically active (i.e., charged as opposed to neutral) dopant atoms to allow it to terminate the electric field of the depletion region. The back surface of the crystalline semiconductor substrate, or the interface between the substrate and overlayers formed upon the back surface of the substrate to enhance the backside conductivity or to reduce reflection of incident photons, is a region where the crystal structure of the substrate is imperfectly terminated. Such regions may be capable of generating high leakage currents. If the electric field penetrates the BEL and reaches such an interface, it will efficiently collect the current generated there. Similarly, the electric field will collect leakage current generated by impurities or defects within the BEL. Undepleted regions in the BEL typically are highly-doped and will not be efficient leakage generators. Deep level impurities and defects in depleted regions of the BEL, on the other hand, may generate large leakage currents. If the BEL does not exhibit long minority carrier lifetimes, the BEL may therefore degrade the leakage current of the photodiodes.

Edge leakage currents are usually suppressed by providing guard structures surrounding the array of pixels. These structures collect the leakage currents generated at the diced edges before it reaches the pixels themselves.

SUMMARY

The present invention comprises fabrication of ultra-low leakage current backside-illuminated photodiode arrays wherein the transparent, conducting bias electrode layer is formed so high-temperature processing of the substrate is avoided after the wafer has been gettered. As a consequence, the component of the reverse-bias leakage current associated with strain, crystallographic defects or impurities introduced during elevated temperature processing subsequent to gettering can be kept extremely low. An optically transparent, conductive bias electrode layer, serving as both an optical window and a backside equipotential contact surface for the photodiodes, is fabricated by etching through the polysilicon gettering layer to a thin, heavily-doped crystalline silicon layer formed within the back of the substrate during the gettering process. As discussed above, a structure that simultaneously provides a transparent window and a conductive contact over the same area of the substrate, is important in the case of fully depleted photodiodes and photodiode arrays. An electrical contact formed only around the periphery of the pixel area(s) would not be able to conduct the reverse-bias leakage current generated in the interior of the pixel area. It would therefore be unable to maintain full depletion.

Photodiode arrays fabricated according to this method, and the bias electrode layers of these arrays, are mechanically, electrically and optically superior to the prior art. Bias electrode layers formed in accordance with this method are internal (native), monocrystalline, homostructural layers formed within the semiconductor substrate. The interface between the BEL and the adjoining high-resistivity substrate material does not terminate the crystalline lattice of the substrate, as is the case when the BEL is a polycrystalline layer or a thin metal layer. Interfaces produced by the present method are inherently superior to those produced when the BEL is formed by epitaxy; it is impossible to completely eliminate crystallographic defects and interfacial impurities at epitaxial interfaces.

Bias electrode layers formed according to the present invention have high minority carrier lifetimes. Photocarriers generated therein may be efficiently collected by the depletion regions beneath the gates. Therefore, these BELs can be far thicker than those fabricated using prior art. BEL thicknesses of rough order of magnitude 0.25 to 1.0 micrometer formed in silicon substrates exhibit high external quantum efficiency and low leakage currents. Such BELs are far less susceptible to damage than those with thicknesses of rough order of magnitude 0.01 micrometer formed using prior techniques.

DESCRIPTION OF DRAWINGS

These and other features and advantages of the invention will become more apparent upon reading the following detailed description and upon reference to the accompanying drawings.

FIG. 1 illustrates a backside-illuminated photodiode structure prior to backside thinning according to one embodiment of the invention.

FIG. 2 illustrates a backside-thinned photodiode array structure according to one embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

In one embodiment of the present invention, the heavily-doped polysilicon gettering layer is etched away at approximately room temperature after wafer gettering has been accomplished. This forms an internal (native), optically transparent, conductive, homostructural bias electrode layer from the crystalline layer, doped by dopant diffusion during the gettering process, that remains within the original substrate. The bias electrode layer thus formed provides a transparent, conductive, internal ohmic contact to the photodiode pixels. Part of the crystalline doped layer may be removed during this process to optimize the sheet resistivity of the contact layer.

Referring to FIG. 1, the low-leakage current backside-illuminated photodiode array structure 100 is formed within a high-resistivity silicon substrate 110 of a first conductivity type. For illustrative purposes, the substrate may be taken to be n-type. Using conventional semiconductor processing techniques, an array of heavily-doped gate regions 120 of a second, opposite conductivity type, is formed near the front surface 130 of the substrate 110. Additional doped regions 140, each of which may have the same conductivity type as the substrate 110 or the opposite conductivity type, may be formed for purposes other than fabrication of the photodiode array itself.

Additional low- or high-temperature process (e.g., growth or deposition of oxides or other dielectric layers, chemical or plasma etching, dopant deposition, diffusion, ion implantation) may be performed as part of the process of defining the frontside structures of the photodiode array or ancillary devices.

Subsequent to the final high-temperature process, a polysilicon layer 150 is deposited on the back surface 160 of the substrate 110. The polysilicon layer 150 may have a thickness in the rough order of magnitude of 0.25 to 1.5 micrometers. The polysilicon layer 150 is heavily doped by incorporation of impurities of the same conductivity type as the substrate 110. Polysilicon doping may be performed in situ during deposition or subsequently by deposition of a dopant source layer (e.g., POCl₃ for n-type substrates) or other means. The photodiode structure 100 is then subjected to a high-temperature thermal gettering cycle to transport crystallographic defects and unintentional impurities into the doped polysilicon layer 150. During the gettering process, which may involve oxidation of the front or back surfaces of the photodiode structure 100, dopant atoms from the polysilicon layer 150 may diffuse into the back regions of the substrate 110, forming a heavily-doped internal (native), homostructural, crystalline layer 170 within the substrate 110. The backside diffused layer 170 may initially have a thickness of rough order of magnitude 0.5 to 5 micrometers, a maximum carrier concentration of rough order of magnitude 1×10²⁰ cm⁻³, and a sheet resistivity of rough order of magnitude 2 to 20Ω per square.

Following the gettering process, the doped polysilicon layer 150 and part of the backside diffused layer 170 are removed. Removal of the polysilicon gettering layer 150 and the portion of the backside diffused layer 170 may be accomplished by wet-chemical etching, ion-assisted etching (plasma or reactive-ion etching) singly or in combination, or by other means.

The backside diffused layer 170 is thinned to a final thickness compatible with high external quantum efficiency, low leakage current, and conductivity adequate to facilitate uniform backside biasing. The backside diffused layer 170 may have a final thickness of rough order of magnitude range of 0.25 to 1.0 micrometers and a sheet resistivity in the approximate range of 50 to 1000Ω per square.

Referring to FIG. 2, the backside-thinned photodiode array structure 200 includes all the frontside layers, interfaces and other features as the unfinished photodiode structure 170 of FIG. 1. Additional layers, interfaces or features may be formed upon the front surface 130 of the substrate 110 prior to backside thinning, to provide external contacts to the gates 120 or additional doped layers 140, to provide readout circuits, or for other purposes. The backside-thinned photodiode array 200 includes a thinned backside diffused layer 270 that forms the bias electrode layer for the photodiode array structure. The thinning process also creates a new back surface 260 on the substrate 110.

Subsequent to backside thinning, one or more additional external (non-native) layers 280 may be formed over the new back surface 260 to decrease the reflectivity of the structure at the optical wavelengths of interest or to enhance the backside conductivity of the structure. In contrast to the ultra-thin backside contact structures employed in the prior art, the thick, robust bias electrode layers 270 of the backside-thinned structure 200 are sufficiently conductive to render such conductivity enhancement unnecessary. Therefore, a wide choice of single- or multi-layer dielectric anti-reflective coating structures may be used to optimize the external quantum efficiency of the photodiode array. Such optimization is not usually possible in the prior art, because there is a very limited selection of transparent conductive layers such as indium-tin oxide [ITO] that can be used to enhance the back surface conductivity. These materials, therefore, afford a similarly limited choice of optical properties to be used in designing conductive, anti-reflective coating structures. In general, photodiode arrays equipped with anti-reflection coating structures formed using transparent conductors will exhibit higher reflectivities than those using properly-designed dielectric anti-reflection coating structures.

The method described herein has been employed to fabricate 16-element (4×4 pixel square) silicon photodiode arrays with approximately 9 mm² (3 mm×3 mm) pixel areas used in a commercially available gamma-ray imaging system. These devices exhibit high external quantum efficiencies—over 90% at 560 nm wavelength—when equipped with single- or multi-layer dielectric anti-reflection coatings. Production devices routinely exhibit reverse-bias leakage currents below 1 nA/cm⁻² at room temperature.

A number of embodiments of the invention have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the invention. Accordingly, other embodiments are within the scope of the following claims. 

1. A backside illuminated diode, comprising: a optically transparent substrate of a first conductivity type, and defining first and second homostructural regions, the first homostructural region near a front surface, and the second homostructural region near the rear surface being a conductive region which is more conductive than the first homostructural region being less conductive; at least one structure of a second conductivity type, in contact with said substrate of said first conductivity type, forming at least one PN junction therein of a type adapted to convert incoming light into an electrical signal indicative thereof.
 2. A diode as in claim 1, further comprising a first electrical connection to said second homostructural layer to apply a bias thereto.
 3. A diode as in claim 1, wherein said second portion of said second conductivity type has a sheet resistivity between 2 and 20 Ω per square.
 4. A diode as in claim 1, wherein said first portion and said second portion have a substantially continuous crystalline structure therebetween.
 5. A diode as in claim 1, wherein said second region is one which has not been subjected to any high temperature processing.
 6. A diode as in claim 1, wherein an interface between the first and second regions does not terminate a crystalline lattice within the substrate.
 7. A diode as in claim 1, further comprising an anti-reflective coating, formed on said rear surface.
 8. A diode as in claim 7, wherein said anti-reflective coating is formed of multiple layers of dielectric material.
 9. A method, comprising: forming a backside illuminated diode from a single structural substrate having first and second homostructural portions, the second homostructural portion forming a conductive layer for biasing the diode and the second homostructural portion being adjacent the backside of the diode; forming at least one PN junction in the first homo structural portions; and using the diode by illuminating the diode from its backside and receiving signals therefrom indicative of said illuminating.
 10. A method as in claim 9, further comprising coating the backside with an anti-reflective coating.
 11. A method as in claim 10, wherein said coating comprises coating the rear surface with multiple layers of dielectric material.
 12. A method of forming a backside illuminated diode comprising: forming a semiconductor substrate from a silicon material; gettering the semiconductor substrate at a high temperature using a gettering layer; removing the entire gettering layer; and using a remaining portion of the silicon substrate as a bias electrode layer for the backside illuminated diode.
 13. A method as in claim 12, wherein said using comprises using said the backside layer without carrying out any high temperature process subsequent to said gettering.
 14. A method as in claim 13, further comprising forming an optically transparent bias electrode layer during said gettering, within the semiconductor substrate.
 15. A method as in claim 14, wherein said forming comprises forming a bias electrode layer which has crystalline lattice which is consistent with a crystalline structure of a remaining portion of the substrate.
 16. A method as in claim 12, further comprising thinning said remaining portion prior to using said remaining portion as a bias electrode layer.
 17. A method as in claim 12, wherein said removing uses at least one of wet chemical etching; plasma ion assisted etching, or reactive ion etching.
 18. A method as in claim 17, wherein said removing is carried out at substantially room temperature.
 19. A method as in claim 16, wherein said thinning thins said remaining portion to a thickness between 0.25 and 1 μm.
 20. A method as in claim 12, further comprising applying an anti-reflective coating over said remaining portion.
 21. A method as in claim 20, wherein said anti-reflective coating comprises a dielectric anti-reflective coating.
 22. A method as in claim 21, wherein said anti-reflective coating comprises a plurality of separate dielectric anti-reflection coating.
 23. A backside illuminated diode, comprising: a semiconductor substrate having a front surface and a rear surface, having at least one structure adjacent the front surface that is of an opposite conductivity type to a conductivity type of the bulk of the substrate, and having said rear surface which forms a bias electrode layer which is an optically transparent conductive layer, said semiconductor substrate having a continuous crystalline lattice extending from said front surface to said rear surface.
 24. A diode as in claim 23, wherein said second portion has a thickness less than 1 μm.
 25. A diode as in claim 23, further comprising an anti-reflection coating, coated on said rear surface.
 26. A diode as in claim 25, wherein said anti-reflection coating is formed of a dielectric material.
 27. A diode as in claim 26, wherein said anti-reflection coating is formed of multiple layers of dielectric materials.
 28. A diode as in claim 23, wherein said substrate has an N conductivity type.
 29. A diode as in claim 23, wherein said at least structure comprises a plurality of gates.
 30. A diode as in claim 23, wherein said substrate is formed of silicon.
 31. A method, comprising: forming a optically transparent semiconductor substrate of a first conductivity type; front surface processing said semiconductor substrate to add at least one gate of a second conductivity type; rear surface processing a rear surface of the semiconductor substrate to convert a region of the rear substrate into a bias electrode portion that is conductive and is homostructural with said semiconductor substrate.
 32. A method as in claim 31, wherein after forming said bias electrode portion, no further high temperature processes are carried out.
 33. A method as in claim 32, wherein said after said forming, all processes are carried out at substantially room temperature.
 34. A method as in claim 31, wherein said rear surface processing comprises gettering the semiconductor substrate to form said structural bias electrode portion within said substrate, and removing the gettering layer without a high temperature process.
 35. A method as in claim 34, wherein said removing the gettering layer comprises removing the gettering layer at substantially room temperature.
 36. A method as in claim 34, wherein said gettering comprises applying a doped polysilicon layer to a rear surface of the substrate, causing dopant atoms from the polysilicon layer to diffuse into back regions of the substrate adjacent to said rear surface, to form a defuse portion within an area adjacent said rear surface.
 37. A method as in claim 36, wherein said diffused portion near said rear surface has a carrier concentration of 1020 cm-3.
 38. A method as in claim 36, further comprising removing said doped polysilicon layer using a non-hightemperature process.
 39. A method as in claim 38, wherein said non-high temperature process is a room temperature process.
 40. A method as in claim 38, wherein said non-high temperature process is one of wet chemical etching, plasma ion assisted etching, or reactive ion assisted etching or a combination thereof.
 41. A method as in claim 38, wherein said removing further comprises removing at least a portion of said it diffused portion.
 42. A method as in claim 41, wherein said removing comprises removing a portion leaving a final thickness between 0.25 and 1.0 μm.
 43. A method as in claim 41, further comprising, after said removing, adding an anti-reflective coating.
 44. A method as in claim 43, wherein said anti-reflective coating is a dielectric coating.
 45. A method as in claim 44, wherein said anti-reflective coating is a dielectric coating formed of multiple different dielectric layers.
 46. A method, comprising: using an optically transparent substrate with a non-terminated crystalline lattice as a backside illuminated diode by applying an electrical bias to a backside portion, and detecting light near a front side portion.
 47. A method as in claim 46, further comprising changing a portion of said substrate to form a homostructural bias electrode portion operating to receive said electrical bias.
 48. A method as in claim 47, wherein after forming said bias electrode portion, no further high temperature processes are carried out.
 49. A method as in claim 48, wherein said after said forming, all processes are carried out at substantially room temperature.
 50. A method as in claim 47, wherein said changing comprises gettering the semiconductor substrate to form said bias electrode portion within said substrate, and removing the gettering layer without a high temperature process.
 51. A method as in claim 50, wherein said removing the gettering layer comprises removing the gettering layer at substantially room temperature.
 52. A method as in claim 50, wherein said gettering comprises applying a doped polysilicon layer to a rear surface of the substrate, causing dopant atoms from the polysilicon layer to diffuse into back regions of the substrate adjacent to said rear surface, to form a diffused portion within an area adjacent said rear surface.
 53. A method as in claim 52, wherein said diffused portion near said rear surface has a carrier concentration of 1020 cm-3.
 54. A method as in claim 52, further comprising removing said doped polysilicon layer using a non-hightemperature process.
 55. A method as in claim 54, wherein said removing further comprises removing at least a portion of said diffused portion.
 56. A method as in claim 55, wherein said removing comprises removing a portion leaving a final thickness between 0.25 and 1.0 μm.
 57. A method as in claim 55, further comprising, after said removing, adding an anti-reflective coating.
 58. A method as in claim 57, wherein said anti-reflective coating is a dielectric coating.
 59. A method as in claim 58, wherein said anti-reflective coating is a dielectric coating formed of multiple different dielectric layers.
 60. A backside illuminated diode comprising: a single continuous piece of substantially optically transparent semiconductor material, having a rear conductive surface, and a front surface with at least one PN junction adjacent thereto.
 61. A diode as in claim 60, further comprising an anti-reflection coating, coated on said rear surface.
 62. A diode as in claim 61, wherein said anti-reflection coating is formed of a dielectric material.
 63. A diode as in claim 62, wherein said anti-reflection coating is formed of multiple layers of dielectric materials.
 64. A diode as in claim 60, wherein said semiconductor material is of an N conductivity type.
 65. A backside illuminated diode, comprising: a optically transparent substrate of a first conductivity type, and defining first and second homostructural regions, the first homostructural region extending to a front surface, and the second homostructural region extending to a rear surface and being sufficiently conductive region to enable a bias to be applied thereto, and said first homostructural region being less conductive, and wherein said first portion and said second portion have a substantially continuous crystalline structure therebetween which is not terminated; at least one structure of a second conductivity type, in contact with said substrate of said first conductivity type, forming at least one PN junction therein of a type adapted to convert incoming light into a signal.
 66. A diode as in claim 65, further comprising a first electrical connection to said second homostructural layer to apply a bias thereto.
 67. A diode as in claim 65, wherein said second portion of said second conductivity type has a sheet resistivity between 2 and 20 Ω per square.
 68. A diode as in claim 65, wherein said second region

one which has not been subjected to any high temperature

ssing after its formation.
 69. A diode as in claim 65, further comprising an anti-reflective coating, formed on said rear surface.
 70. A diode as in claim 69, wherein said anti-reflective coating is formed of multiple layers of dielectric material. 